WEBVTT 00:00:00.000 --> 00:00:02.640 Welcome to this deep dive. You know, this show 00:00:02.640 --> 00:00:05.599 takes a stack of your sources, articles, research, 00:00:05.639 --> 00:00:08.699 your own notes, and we just extract the most 00:00:08.699 --> 00:00:10.939 important nuggets of knowledge. Yeah, think of 00:00:10.939 --> 00:00:13.460 it as like your personal shortcut to being well 00:00:13.460 --> 00:00:17.160 informed. Exactly. And today we have a custom 00:00:17.160 --> 00:00:19.719 deep dive tailored specifically for you, the 00:00:19.719 --> 00:00:23.260 listener. We are exploring a single, honestly 00:00:23.260 --> 00:00:26.440 wildly fascinating Wikipedia article on something 00:00:26.440 --> 00:00:29.219 called three state logic. It sounds super technical. 00:00:29.289 --> 00:00:31.010 I know, but it's actually everywhere. Right. 00:00:31.070 --> 00:00:34.530 And to set the stage, I want you to picture a 00:00:34.530 --> 00:00:37.990 massive busy city intersection, like six lanes 00:00:37.990 --> 00:00:40.310 of traffic in every single direction. OK, I'm 00:00:40.310 --> 00:00:42.369 picturing it. Now imagine there is zero traffic 00:00:42.369 --> 00:00:44.850 lights, no stop signs, and literally everyone 00:00:44.850 --> 00:00:47.149 is driving at top speed. Oh, wow. I mean, that's 00:00:47.149 --> 00:00:50.530 just total instantaneous chaos, wreckage everywhere. 00:00:50.670 --> 00:00:53.289 Pure chaos. And that interception is exactly 00:00:53.289 --> 00:00:55.450 what the inside of your computer or your smartphone 00:00:55.450 --> 00:00:57.670 or even your digital microwave would look like 00:00:57.670 --> 00:01:00.409 without this secret. hidden third state of digital 00:01:00.409 --> 00:01:02.469 electronics. Because we've all been taught the 00:01:02.469 --> 00:01:04.530 exact same thing, right? From the very first 00:01:04.530 --> 00:01:07.129 time you take a computer class, you are fed a 00:01:07.129 --> 00:01:09.549 very specific myth. Yeah, that computers run 00:01:09.549 --> 00:01:13.069 entirely on binary. Just ones and zeros on and 00:01:13.069 --> 00:01:15.409 off. Right. High voltage and low voltage. And 00:01:15.409 --> 00:01:18.390 I mean, it is a very comforting, very straightforward 00:01:18.390 --> 00:01:20.689 way to view the digital world. You either have 00:01:20.689 --> 00:01:23.540 power or you don't. OK, let's unpack this. We 00:01:23.540 --> 00:01:26.939 have our standard binary logic, a high voltage 00:01:26.939 --> 00:01:30.359 output state, which represents a logical one. 00:01:30.439 --> 00:01:33.599 Yeah. and a low outfit state representing a logical 00:01:33.599 --> 00:01:37.920 zero. So what on earth is the third state? Because 00:01:37.920 --> 00:01:40.040 you currently have half a voltage in pure digital 00:01:40.040 --> 00:01:42.799 logic. No, you can't. In digital electronics, 00:01:43.239 --> 00:01:45.299 this third state is actually called high impedance. 00:01:46.260 --> 00:01:49.060 It's typically abbreviated in engineering as 00:01:49.060 --> 00:01:51.700 high Z. High Z. OK. And the crucial thing to 00:01:51.700 --> 00:01:53.359 understand right out of the gate is that high 00:01:53.359 --> 00:01:55.980 Z isn't a voltage level at all. Wait, really? 00:01:55.980 --> 00:01:58.719 The article uses that term, impedance. But let's 00:01:58.719 --> 00:02:00.439 translate that into plain English for a second. 00:02:00.640 --> 00:02:03.819 What is impedance physically doing? So think 00:02:03.819 --> 00:02:06.799 of impedance simply as electrical resistance. 00:02:07.780 --> 00:02:10.379 When a device enters the high impedance state, 00:02:10.599 --> 00:02:13.560 or high Z, it's essentially throwing up a massive 00:02:13.560 --> 00:02:16.639 impenetrable wall of resistance. Oh, I see. The 00:02:16.639 --> 00:02:19.800 resistance is so incredibly high that electricity 00:02:19.800 --> 00:02:22.900 simply cannot flow through the gate. The output 00:02:22.900 --> 00:02:26.300 of that component is effectively like physically 00:02:26.300 --> 00:02:28.379 disconnected from the rest of the circuit. So 00:02:28.379 --> 00:02:30.759 it behaves exactly like an open switch. Exactly 00:02:30.759 --> 00:02:33.460 like an open switch. So if a logical one is say 00:02:33.460 --> 00:02:36.860 someone standing in a room shouting and a logical 00:02:36.860 --> 00:02:39.539 zero is someone in that same room whispering. 00:02:40.199 --> 00:02:43.340 Hi -Z isn't just staying quiet. Hi -Z is leaving 00:02:43.340 --> 00:02:45.919 the room entirely, locking the door, and basically 00:02:45.919 --> 00:02:48.639 ceasing to exist as far as the room is concerned. 00:02:48.840 --> 00:02:51.139 What's fascinating here is that analogy perfectly 00:02:51.139 --> 00:02:54.099 captures the physics of the situation. It's the 00:02:54.099 --> 00:02:56.919 absolute removal of a device's electrical influence 00:02:56.919 --> 00:02:59.319 from the shared circuit. A state of total disconnection. 00:02:59.419 --> 00:03:01.439 Yeah, intentional disconnection. And to understand 00:03:01.439 --> 00:03:03.699 how engineers actually apply this, your source 00:03:03.699 --> 00:03:05.759 material points us to something called a tri 00:03:05.759 --> 00:03:07.919 -state buffer. Right, I saw that. The article 00:03:07.919 --> 00:03:10.479 details the truth table for this buffer. It's 00:03:10.479 --> 00:03:12.860 a little gateway that relies on an enable signal 00:03:12.860 --> 00:03:14.919 to actually function. Right, because a standard 00:03:14.919 --> 00:03:17.340 buffer just takes an incoming signal and passes 00:03:17.340 --> 00:03:19.419 it directly to the output. Just a straight pass 00:03:19.419 --> 00:03:22.099 through. Yeah. But a tri -state buffer has an 00:03:22.099 --> 00:03:24.930 extra pin. this enable signal you just mentioned. 00:03:25.490 --> 00:03:28.229 When that enable signal is turned off, the buffer's 00:03:28.229 --> 00:03:31.349 output slams right into that high Z state. It 00:03:31.349 --> 00:03:33.449 literally vanishes from the circuit. It leaves 00:03:33.449 --> 00:03:35.789 the room. It leaves the room. But when the enable 00:03:35.789 --> 00:03:38.509 signal is turned on, the buffer wakes up and 00:03:38.509 --> 00:03:41.729 acts like a regular gateway. It duplicates the 00:03:41.729 --> 00:03:44.530 input, whether that's a one or a zero. and pushes 00:03:44.530 --> 00:03:46.330 it through to the output. Now, I have to push 00:03:46.330 --> 00:03:48.610 back on something here, because the text mentions 00:03:48.610 --> 00:03:51.389 a secondary feature of this buffer that, honestly, 00:03:51.530 --> 00:03:53.389 it confused me at first. Yeah, with the restoration 00:03:53.389 --> 00:03:56.569 part. Yeah. It says that when this buffer is 00:03:56.569 --> 00:03:58.870 enabled, it doesn't just lazily pass the one 00:03:58.870 --> 00:04:02.189 or the zero along. It actually provides voltage 00:04:02.189 --> 00:04:05.110 -level restoration. Yes. But why does a digital 00:04:05.110 --> 00:04:07.650 signal need restoring? I mean, if I pass you 00:04:07.650 --> 00:04:10.050 a perfectly good one, shouldn't you just pass 00:04:10.050 --> 00:04:12.669 a one to the next component? Well, that is where 00:04:12.669 --> 00:04:15.289 the pristine mathematical theory of ones and 00:04:15.289 --> 00:04:18.810 zeros violently collides with the messy, harsh 00:04:18.810 --> 00:04:21.990 reality of analog physics. Oh, right. Physics 00:04:21.990 --> 00:04:25.310 ruins everything. Exactly. As an electrical pulse 00:04:25.310 --> 00:04:28.209 travels through microscopic copper wires, across 00:04:28.209 --> 00:04:30.689 solder joints and past other humming components, 00:04:31.329 --> 00:04:34.730 it degrades. It gets tired. A crisp, sharp, 5 00:04:34.730 --> 00:04:37.689 -volt high signal starts to sag and lose energy. 00:04:38.230 --> 00:04:41.329 And a crisp, 0 -volt low signal might pick up 00:04:41.329 --> 00:04:43.750 some ambient electromagnetic interference and 00:04:43.750 --> 00:04:46.389 actually rise slightly. Oh, wow. So they start 00:04:46.389 --> 00:04:48.410 drifting toward the middle. Exactly. And if you 00:04:48.410 --> 00:04:50.189 don't actively clean that up, eventually your 00:04:50.189 --> 00:04:53.430 1 sag so low and your 0 rises so high that the 00:04:53.430 --> 00:04:55.569 receiving chip literally cannot tell them apart. 00:04:55.649 --> 00:04:57.829 Ah, so the tri -state buffer, when it's in the 00:04:57.829 --> 00:04:59.829 room and actively participating, is also acting 00:04:59.829 --> 00:05:02.269 like a signal booster. Precisely. It takes a 00:05:02.269 --> 00:05:05.870 tired, sagging, degraded signal, looks at it 00:05:05.870 --> 00:05:08.050 and says, OK, you're at 3 .8 volts, you're clearly 00:05:08.050 --> 00:05:10.509 supposed to be a 1, and it blasts out a fresh, 00:05:10.810 --> 00:05:13.050 strong, perfectly valid 5 -volt signal to the 00:05:13.050 --> 00:05:15.790 next phase. It guarantees the output is well 00:05:15.790 --> 00:05:18.970 within the valid logic voltage range. Oh. And 00:05:18.970 --> 00:05:21.569 for the sake of thoroughness, your sources also 00:05:21.569 --> 00:05:24.310 note you can get inverting tri -state buffers. 00:05:24.490 --> 00:05:26.829 Which do the same thing, but flip the signal. 00:05:26.949 --> 00:05:29.050 Yeah, they do the exact same restorative boosting, 00:05:29.490 --> 00:05:31.810 but intentionally flip a one to a zero, or vice 00:05:31.810 --> 00:05:33.550 versa, depending on what the circuit actually 00:05:33.550 --> 00:05:36.730 needs. OK, so what does this all mean for how 00:05:36.730 --> 00:05:39.750 our devices actually function? Like, why is this 00:05:39.750 --> 00:05:42.050 ability to completely vanish from the circuit 00:05:42.050 --> 00:05:44.970 so critical? Well, the article immediately points 00:05:44.970 --> 00:05:47.610 to something called shared buses. Right. Think 00:05:47.610 --> 00:05:51.610 of a bus and a computer as a massive multi -lane 00:05:51.610 --> 00:05:55.149 superhighway. of copper wires that connects everything 00:05:55.149 --> 00:05:57.949 together. Like the motherboard. Exactly. Your 00:05:57.949 --> 00:05:59.730 central processing unit, your system memory, 00:05:59.930 --> 00:06:02.610 your graphics card, USB controllers, they were 00:06:02.610 --> 00:06:05.990 all physically soldered onto the exact same set 00:06:05.990 --> 00:06:08.829 of microscopic copper traces. So they literally 00:06:08.829 --> 00:06:11.129 share the exact same physical wires, which instantly 00:06:11.129 --> 00:06:13.430 brings us back to that chaotic intersection analogy, 00:06:13.629 --> 00:06:17.139 right? Or maybe like a crowded telephone party 00:06:17.139 --> 00:06:19.240 line where everyone is just screaming over each 00:06:19.240 --> 00:06:21.860 other. But if they are all physically wired to 00:06:21.860 --> 00:06:25.019 the exact same copper line, what literally stops 00:06:25.019 --> 00:06:27.420 them from all trying to talk at once and blowing 00:06:27.420 --> 00:06:29.680 a fuse? If we connect this to the bigger picture, 00:06:30.220 --> 00:06:33.019 this is where hardware level diplomacy becomes 00:06:33.019 --> 00:06:35.220 a matter of life and death for the machine. Life 00:06:35.220 --> 00:06:38.129 and death. Literally. Imagine if we only had 00:06:38.129 --> 00:06:41.410 our standard 1s and 0s with no high Z state. 00:06:42.129 --> 00:06:44.689 Device A needs to send a 1, so it floods the 00:06:44.689 --> 00:06:47.189 shared wire with high voltage. But at the exact 00:06:47.189 --> 00:06:50.029 same millisecond, Device B decides to send a 00:06:50.029 --> 00:06:52.970 0, so it aggressively pulls that exact same wire 00:06:52.970 --> 00:06:55.850 down to ground or low voltage. So they're arm 00:06:55.850 --> 00:06:57.889 wrestling over the exact same piece of copper. 00:06:58.009 --> 00:06:59.850 And the loser of that arm wrestling match is 00:06:59.850 --> 00:07:02.199 your computer. That direct fight between high 00:07:02.199 --> 00:07:04.500 and low voltage is the textbook definition of 00:07:04.500 --> 00:07:07.699 a short circuit. The high voltage flows unimpeded 00:07:07.699 --> 00:07:10.360 directly into the low voltage pin. You get a 00:07:10.360 --> 00:07:13.079 massive excessive current draw. And what happens 00:07:13.079 --> 00:07:17.100 to the data? The actual data on the wire is completely 00:07:17.100 --> 00:07:19.740 destroyed. The voltage just hovers somewhere 00:07:19.740 --> 00:07:22.740 in the middle as pure useless noise. And those 00:07:22.740 --> 00:07:27.040 tiny silken... pathways generate incredible instantaneous 00:07:27.040 --> 00:07:29.480 heat. They literally burn up. They burn out completely. 00:07:30.019 --> 00:07:33.339 And that is why we physically cannot build complex 00:07:33.339 --> 00:07:36.100 modern printed circuit boards without the high 00:07:36.100 --> 00:07:38.579 impedance state. So it's fundamentally necessary. 00:07:38.800 --> 00:07:42.259 Absolutely. On a shared bus, every single device 00:07:42.259 --> 00:07:45.339 sits securely behind a tri -state buffer. When 00:07:45.339 --> 00:07:47.439 your computer's CPU needs to read a file from 00:07:47.439 --> 00:07:50.980 memory, the memory chip enables its buffer, drives 00:07:50.980 --> 00:07:53.040 the bus with its data. And everyone else gets 00:07:53.040 --> 00:07:55.639 out of the way. Exactly. Every single other device 00:07:55.639 --> 00:07:58.040 on that entire shared highway goes into high 00:07:58.040 --> 00:08:00.360 Z mode. They all pull over, turn off their engines, 00:08:00.459 --> 00:08:02.319 and leave the highway so the memory chip gets 00:08:02.319 --> 00:08:05.160 a completely clear road. No crosstalk, no noise, 00:08:05.259 --> 00:08:07.139 no short circuits. That's amazing. The source 00:08:07.139 --> 00:08:09.439 highlights a phenomenal real -world example of 00:08:09.439 --> 00:08:12.160 this too. The serial peripheral interface bus. 00:08:12.410 --> 00:08:15.889 Or SPI. OK, how does SPI use it? In a multi -drop 00:08:15.889 --> 00:08:19.449 SPI setup, you have one master controller chip 00:08:19.449 --> 00:08:22.470 talking to multiple peripheral chips, all sharing 00:08:22.470 --> 00:08:24.870 the same communication lines. Right. To prevent 00:08:24.870 --> 00:08:27.829 that catastrophic short circuit, the master uses 00:08:27.829 --> 00:08:31.089 a dedicated pin for each peripheral called chip 00:08:31.089 --> 00:08:34.289 select, or CS. So it's like a teacher in a classroom. 00:08:34.929 --> 00:08:37.830 The master chip taps one specific peripheral 00:08:37.830 --> 00:08:40.610 chip on the shoulder using the CS pin and says, 00:08:40.870 --> 00:08:44.570 you. Talk. Perfect analogy. And because all the 00:08:44.570 --> 00:08:46.149 other chips in the room don't have their CS pin 00:08:46.149 --> 00:08:48.889 activated, their outputs remain strictly in the 00:08:48.889 --> 00:08:52.070 high Z state. They physically cannot interrupt. 00:08:52.450 --> 00:08:54.990 It is brilliant hardware design. And this ability 00:08:54.990 --> 00:08:57.509 to selectively vanish isn't just for massive 00:08:57.509 --> 00:09:00.029 expensive computer motherboards either. It's 00:09:00.029 --> 00:09:02.029 used everywhere. Like where else? Have you ever 00:09:02.029 --> 00:09:04.370 looked at a tiny digital clock or a custom keyboard 00:09:04.370 --> 00:09:06.669 and wondered how it can light up hundreds of 00:09:06.669 --> 00:09:09.100 individual LEDs? Even though the cheap little 00:09:09.100 --> 00:09:11.000 microchip controlling them only has a handful 00:09:11.000 --> 00:09:13.279 of physical pins. Actually, yeah. I've always 00:09:13.279 --> 00:09:15.500 assumed it was some sort of rapid -fire optical 00:09:15.500 --> 00:09:18.379 illusion, like some multiplexing trick. You are 00:09:18.379 --> 00:09:20.879 definitely on the right track. The source mentions 00:09:20.879 --> 00:09:23.139 a specific technique called Charlie Plexing. 00:09:23.299 --> 00:09:25.759 Charlie Plexing, okay. Imagine a grid of LEDs. 00:09:26.539 --> 00:09:29.120 If you want to light up just one specific bulb 00:09:29.120 --> 00:09:31.460 in the middle of the grid, you need to send a 00:09:31.460 --> 00:09:34.419 high voltage to its row and a low voltage to 00:09:34.419 --> 00:09:36.990 its column. Right, creating a path for the electricity 00:09:36.990 --> 00:09:40.490 to flow through that one specific LED. But electricity 00:09:40.490 --> 00:09:43.370 is notoriously lazy, and it will try to find 00:09:43.370 --> 00:09:46.029 sneak paths through the other surrounding LEDs 00:09:46.029 --> 00:09:49.029 in the grid, faintly lighting up bulbs you actually 00:09:49.029 --> 00:09:51.149 want to remain dark. Oh, and in the light. Yeah. 00:09:51.850 --> 00:09:54.470 So Charlie Plexing solves this by utilizing our 00:09:54.470 --> 00:09:57.799 third state. The microchip rapidly switches the 00:09:57.799 --> 00:10:00.419 pins controlling the other rows and columns into 00:10:00.419 --> 00:10:03.080 the disconnected high Z state. Oh, wow. So by 00:10:03.080 --> 00:10:05.200 going into high impedance, it essentially acts 00:10:05.200 --> 00:10:07.419 like a pair of scissors, temporarily snipping 00:10:07.419 --> 00:10:09.679 the wires of those alternate paths. Yes. The 00:10:09.679 --> 00:10:11.419 electricity has literally nowhere else to go 00:10:11.419 --> 00:10:13.639 except through the one specific LED you targeted. 00:10:13.820 --> 00:10:15.840 It forces the current down the single correct 00:10:15.840 --> 00:10:19.320 path. It's this incredibly fast microscopic dance 00:10:19.320 --> 00:10:22.220 of connecting and disconnecting. And speaking 00:10:22.220 --> 00:10:24.620 of that microscopic choreography, here's where 00:10:24.620 --> 00:10:27.039 it gets really interesting in your source material. 00:10:27.159 --> 00:10:28.860 Oh, I know where you're going with this. Yeah. 00:10:29.559 --> 00:10:32.820 When we talk about memory chips like RAM or ROM 00:10:32.820 --> 00:10:35.679 sharing these communication buses, the article 00:10:35.679 --> 00:10:39.259 reveals a fascinating, deeply elegant trade -off 00:10:39.259 --> 00:10:42.840 between speed and power consumption. The subtle 00:10:42.840 --> 00:10:45.659 but vital difference between chip select and 00:10:45.659 --> 00:10:48.539 output enable. Yes, because the article points 00:10:48.539 --> 00:10:51.700 out that many memory devices have both a CS pin 00:10:51.700 --> 00:10:54.820 chip select and an OE pin output enable. Right. 00:10:54.820 --> 00:10:57.000 And if you just glance at the spec sheet, they 00:10:57.000 --> 00:10:59.600 seem completely redundant. I mean, if either 00:10:59.600 --> 00:11:02.059 of those pins is turned off, the chip's output 00:11:02.059 --> 00:11:05.039 goes into that disconnected Hi -Z state. Why 00:11:05.039 --> 00:11:06.960 do you need two different off switches? Because 00:11:06.960 --> 00:11:09.179 how they achieve that disconnection internally 00:11:09.179 --> 00:11:11.440 is radically different. It's honestly a master 00:11:11.440 --> 00:11:13.840 class in engineering optimization. Let's break 00:11:13.840 --> 00:11:16.100 it down for the listener. When chip When the 00:11:16.100 --> 00:11:17.539 memory select is turned off, like when it is 00:11:17.539 --> 00:11:20.259 de -azerted, the article says the chip basically 00:11:20.259 --> 00:11:22.720 goes into a deep sleep. Right, it powers down 00:11:22.720 --> 00:11:25.399 its internal circuitry. Which is fantastic for 00:11:25.399 --> 00:11:28.200 battery life. Yeah, if a memory chip isn't currently 00:11:28.200 --> 00:11:31.019 needed, you definitely want it asleep. But there 00:11:31.019 --> 00:11:33.460 is a massive penalty for that power saving. About 00:11:33.460 --> 00:11:36.240 a wake up time. Exactly. When you finally turn 00:11:36.240 --> 00:11:39.100 that chip select back on, the chip has to wake 00:11:39.100 --> 00:11:42.840 up, stabilize its internal power, receive the 00:11:42.840 --> 00:11:45.080 address of the data you requested, physically 00:11:45.080 --> 00:11:47.639 locate that data deep within its vast memory 00:11:47.639 --> 00:11:50.059 array, and then route it all the way to the exit 00:11:50.059 --> 00:11:52.139 gate. That's a lot of steps. It creates a huge 00:11:52.139 --> 00:11:54.440 latency delay. OK, I want to try an analogy here 00:11:54.440 --> 00:11:57.120 to see if I've got this. Is chip select like 00:11:57.120 --> 00:12:00.600 turning your kitchen oven completely off to save 00:12:00.600 --> 00:12:03.519 electricity? OK, yeah. You save power, but when 00:12:03.519 --> 00:12:05.679 you want to bake a cake, you have to wait 20 00:12:05.679 --> 00:12:07.899 minutes for the oven to preheat from cold. Right. 00:12:08.399 --> 00:12:11.419 Whereas output enable is like, keeping the oven 00:12:11.419 --> 00:12:14.840 on, fully baking the cake, but just keeping the 00:12:14.840 --> 00:12:17.779 oven door closed and locked until the exact second 00:12:17.779 --> 00:12:20.340 you are ready to serve it. That analogy perfectly 00:12:20.340 --> 00:12:23.419 captures the mechanism. If you only rely on chip 00:12:23.419 --> 00:12:26.000 select, you are forcing the computer to wait 00:12:26.000 --> 00:12:27.860 for the oven to preheat every single time it 00:12:27.860 --> 00:12:30.259 needs a piece of data. Which is super slow. But 00:12:30.259 --> 00:12:32.659 if you assert chip select, meaning you turn the 00:12:32.659 --> 00:12:35.159 chip fully on, but you keep the output enable 00:12:35.159 --> 00:12:38.320 pin deserted, the chip is wide awake and working 00:12:38.320 --> 00:12:40.480 furiously. It's baking the cake. It's baking 00:12:40.480 --> 00:12:42.919 the cake. It receives the address from the CPU. 00:12:43.179 --> 00:12:45.720 It finds the data. It routes that data all the 00:12:45.720 --> 00:12:48.340 way to the final exit door. But because output 00:12:48.340 --> 00:12:50.980 enable is off, that final door is locked in a 00:12:50.980 --> 00:12:54.019 high impedance state. Exactly. The chip gets 00:12:54.019 --> 00:12:56.940 everything 100 % prepped and just waits patiently 00:12:56.940 --> 00:12:59.519 at the final driver. And here is the genius part. 00:12:59.580 --> 00:13:01.799 What's that? While the memory chip is doing all 00:13:01.799 --> 00:13:04.159 that internal searching, the main system bus 00:13:04.159 --> 00:13:08.159 is totally free. Other components can be furiously 00:13:08.159 --> 00:13:10.500 passing data back and forth across the motherboard. 00:13:10.759 --> 00:13:13.179 Because our memory chip, despite working hard 00:13:13.179 --> 00:13:15.840 internally, is still technically disconnected 00:13:15.840 --> 00:13:18.120 from the shared highway. It's not blocking traffic. 00:13:18.500 --> 00:13:20.639 And then the very millisecond the shared bus 00:13:20.639 --> 00:13:23.519 is clear and the CPU is ready for the data, the 00:13:23.519 --> 00:13:25.720 system asserts the output enable pin. The door 00:13:25.720 --> 00:13:29.159 opens. the Hi -Z door vanishes, and the data 00:13:29.159 --> 00:13:31.360 floods out onto the bus with practically zero 00:13:31.360 --> 00:13:34.679 delay. In fact, if you look at a highly detailed 00:13:34.679 --> 00:13:37.779 spec sheet for a ROM or static RAM chip, they 00:13:37.779 --> 00:13:40.159 literally list two completely separate access 00:13:40.159 --> 00:13:43.809 times to account for this. Let me guess. A painfully 00:13:43.809 --> 00:13:46.570 long time for a chip select wakeup, and a dramatically 00:13:46.570 --> 00:13:48.950 shorter time for an output enable door open. 00:13:49.049 --> 00:13:51.529 You'll see times listed in tens of nanoseconds 00:13:51.529 --> 00:13:54.309 for a full chip select cycle, compared to maybe 00:13:54.309 --> 00:13:56.850 just a few nanoseconds for an output enable cycle. 00:13:57.090 --> 00:14:00.120 That is such a clever way to cheat latency. But 00:14:00.120 --> 00:14:01.899 wait, I have to stop and ask about something 00:14:01.899 --> 00:14:04.200 that feels like a glaring flaw in this entire 00:14:04.200 --> 00:14:07.019 architecture. OK, what is it? We firmly established 00:14:07.019 --> 00:14:10.379 that high Z means disconnected. It's an open 00:14:10.379 --> 00:14:12.980 switch. Yes. If you have a shared bus, and nobody 00:14:12.980 --> 00:14:14.759 is currently selecting, let's say the CPU is 00:14:14.759 --> 00:14:17.480 busy doing math internally, and every single 00:14:17.480 --> 00:14:19.659 peripheral device has left the room and is sitting 00:14:19.659 --> 00:14:22.820 in a high Z state, what physically happens to 00:14:22.820 --> 00:14:25.139 the copper wire itself? Ah. It's just sitting 00:14:25.139 --> 00:14:27.360 there attached to absolutely nothing. This raises 00:14:27.360 --> 00:14:30.519 an important question. And it's a physical reality 00:14:30.519 --> 00:14:32.980 that severely plagued early circuit designers. 00:14:33.559 --> 00:14:36.019 When all the outputs attached to a bus are tristated, 00:14:36.600 --> 00:14:38.899 the circuit node enters what we call a floating 00:14:38.899 --> 00:14:42.019 state. Floating? That sounds... I'm assuming 00:14:42.019 --> 00:14:44.840 floating is bad. Floating is a nightmare in digital 00:14:44.840 --> 00:14:47.799 logic. It really has no defined voltage level 00:14:47.799 --> 00:14:51.700 at all. An unattached copper wire acts exactly 00:14:51.700 --> 00:14:54.759 like a tiny radio antenna. Oh, picking up interference. 00:14:55.000 --> 00:14:58.250 Exactly. Ambient electromagnetic noise. From 00:14:58.250 --> 00:15:00.590 the power supply, from a nearby cell phone, from 00:15:00.590 --> 00:15:02.750 the literal fluorescent lights in the room, can 00:15:02.750 --> 00:15:05.350 cause the voltage on that floating wire to drift 00:15:05.350 --> 00:15:07.409 up and down randomly. And if a component suddenly 00:15:07.409 --> 00:15:09.509 wakes up and samples that line while it's floating? 00:15:10.190 --> 00:15:13.289 It might read a false one or a false zero, causing 00:15:13.289 --> 00:15:15.889 a total system crash. So how do you anchor a 00:15:15.889 --> 00:15:17.389 floating wire? I mean, you have to stabilize 00:15:17.389 --> 00:15:20.009 it somehow. Engineers fix it with something incredibly 00:15:20.009 --> 00:15:23.549 simple. Resistors. Specifically, pull up or pull 00:15:23.549 --> 00:15:25.909 down resistors. Usually somewhere in the range 00:15:25.909 --> 00:15:28.950 of 1 to 100 kilo ohms. Wait, hold on. If the 00:15:28.950 --> 00:15:31.269 line is literally just floating there disconnected, 00:15:31.929 --> 00:15:35.049 how does adding a resistor, which is, you know, 00:15:35.250 --> 00:15:38.230 literally a roadblock for electricity, magically 00:15:38.230 --> 00:15:40.950 create a stable signal? It seems counterintuitive. 00:15:41.250 --> 00:15:42.970 Yeah. Aren't you just making it harder for the 00:15:42.970 --> 00:15:45.809 electricity to flow? Let's visualize it. You 00:15:45.809 --> 00:15:48.570 take the shared bus wire and you tie it directly 00:15:48.570 --> 00:15:51.870 to your main high voltage power source. But you 00:15:51.870 --> 00:15:54.230 put that 10 kilo ohm resistor right in between 00:15:54.230 --> 00:15:56.970 them. OK, I'm visualizing it. If any chip on 00:15:56.970 --> 00:15:59.509 the bus actively wants to drive the line low 00:15:59.509 --> 00:16:02.429 to send a zero, its internal transistors are 00:16:02.429 --> 00:16:04.990 strong enough to easily pull the voltage down, 00:16:05.429 --> 00:16:07.490 completely overpowering the resistor. Because 00:16:07.490 --> 00:16:10.049 the resistor is weak. Right. But when everyone 00:16:10.049 --> 00:16:12.950 goes into high Z and lets go of the line, that 00:16:12.950 --> 00:16:15.769 gentle pull -up resistor acts like a weak spring. 00:16:16.529 --> 00:16:19.070 It slowly, safely pulls the voltage of the floating 00:16:19.070 --> 00:16:22.120 wire up to a default logical one. So it's literally 00:16:22.120 --> 00:16:24.419 like a weak mechanical spring that always pulls 00:16:24.419 --> 00:16:26.679 a door shut when nobody is actively holding it 00:16:26.679 --> 00:16:29.039 open. It guarantees the door is never just like 00:16:29.039 --> 00:16:31.279 flapping in the wind. That's the exact mechanism. 00:16:33.039 --> 00:16:35.539 But as with all things in engineering, solving 00:16:35.539 --> 00:16:38.580 one problem immediately creates a new, more complicated 00:16:38.580 --> 00:16:41.600 one. Of course it does. As computers got faster, 00:16:42.039 --> 00:16:44.080 specifically when the industry moved to things 00:16:44.080 --> 00:16:47.740 like the PCI local bus in the 1990s, this weak 00:16:47.740 --> 00:16:50.700 spring solution simply wasn't fast enough. I 00:16:50.700 --> 00:16:53.419 noticed that. The sources mentioned the PCI bus 00:16:53.419 --> 00:16:56.539 having a large distributed capacitance. Yes. 00:16:56.659 --> 00:16:59.179 What does that mean in plain English, and why 00:16:59.179 --> 00:17:01.820 does it break our weak spring? Well, capacitance 00:17:01.820 --> 00:17:04.559 is essentially the ability of a physical component 00:17:04.559 --> 00:17:07.849 to store an electrical charge. A long copper 00:17:07.849 --> 00:17:10.250 wire running across a motherboard with dozens 00:17:10.250 --> 00:17:13.390 of chips attached to it acts like a tiny unintentional 00:17:13.390 --> 00:17:15.829 battery. Oh I see. It actually takes time to 00:17:15.829 --> 00:17:18.130 fill that wire up with voltage and it takes time 00:17:18.130 --> 00:17:20.849 to drain it. So if you just rely on a weak 10 00:17:20.849 --> 00:17:23.289 kilo ohm resistor to pull the voltage up the 00:17:23.289 --> 00:17:25.430 battery of the long wire just absorbs all that 00:17:25.430 --> 00:17:27.109 weak energy. It's like trying to fill a swimming 00:17:27.109 --> 00:17:28.710 pool with a dripping faucet. That would take 00:17:28.710 --> 00:17:31.650 forever. In the early days that was fine. But 00:17:31.650 --> 00:17:34.750 on a high -speed PCI bus, waiting for that weak 00:17:34.750 --> 00:17:37.190 resistor to fill the wire's capacitance would 00:17:37.190 --> 00:17:39.930 take several full clock cycles. Which ruins the 00:17:39.930 --> 00:17:42.549 speed. Totally. The system would just be sitting 00:17:42.549 --> 00:17:44.730 there waiting for the voltage to slowly drift 00:17:44.730 --> 00:17:47.349 high enough to be recognized as a valid state, 00:17:47.890 --> 00:17:49.609 completely ruining your high -speed operation. 00:17:50.369 --> 00:17:53.950 So how did they fix the dripping faucet? The 00:17:53.950 --> 00:17:56.369 article mentions Intel created a convention called 00:17:56.369 --> 00:17:59.230 sustained tri -state. They essentially changed 00:17:59.230 --> 00:18:01.869 the rules of engagement. The sustained tri -state 00:18:01.869 --> 00:18:04.450 protocol physically requires that whatever device 00:18:04.450 --> 00:18:07.309 is currently talking on the bus must do something 00:18:07.309 --> 00:18:09.829 a bit counterintuitive. What's that? It must 00:18:09.829 --> 00:18:12.130 forcefully drive the control signals to a high 00:18:12.130 --> 00:18:15.490 voltage for at least one full clock cycle before 00:18:15.490 --> 00:18:17.650 it's allowed to enter the disconnected high Z 00:18:17.650 --> 00:18:19.869 state. Wait, really? So the device basically 00:18:19.869 --> 00:18:22.809 has to yell, I'm hanging up, knees no W, by blasting 00:18:22.809 --> 00:18:25.829 the signal high before it disconnects? Yes. It 00:18:25.829 --> 00:18:28.549 actively pre -fills the wire's capacitance by 00:18:28.549 --> 00:18:30.869 using its strong internal transistors to forcefully 00:18:30.869 --> 00:18:33.890 drive the bus high. It rapidly forces the wire 00:18:33.890 --> 00:18:36.670 to the default state in a fraction of a nanosecond. 00:18:36.829 --> 00:18:40.190 And then, and only then, does it drop into high 00:18:40.190 --> 00:18:42.990 Z. That's brilliant. So the weak pull -up resistor 00:18:42.990 --> 00:18:45.190 isn't responsible for changing the voltage of 00:18:45.190 --> 00:18:47.990 the wire anymore. It's only responsible for holding 00:18:47.990 --> 00:18:50.250 it there against minor leakage currents after 00:18:50.250 --> 00:18:52.990 the chip does the heavy lifting. Exactly. It's 00:18:52.990 --> 00:18:55.769 a beautiful workaround for the messy analog physics 00:18:55.769 --> 00:18:59.930 of high -speed wiring. And actually, Intel utilizes 00:18:59.930 --> 00:19:04.769 this exact same sustained tri -state trick on 00:19:04.769 --> 00:19:08.019 the low pin count bus, too. This constant ongoing 00:19:08.019 --> 00:19:10.680 battle between pristine digital logic and the 00:19:10.680 --> 00:19:13.680 messy reality of physical wiring is just amazing. 00:19:13.779 --> 00:19:16.339 It really is. But it also leads us to the final 00:19:16.339 --> 00:19:18.779 major revelation in your source material. Because 00:19:18.779 --> 00:19:21.019 it turns out tristate logic isn't the only way 00:19:21.019 --> 00:19:23.140 to solve this highway traffic jam. No, it's not. 00:19:23.259 --> 00:19:25.829 The article mentions a major alternative. the 00:19:25.829 --> 00:19:27.890 open collective output. And this fundamentally 00:19:27.890 --> 00:19:29.710 changes the rules of the room we've been talking 00:19:29.710 --> 00:19:32.150 about. The most famous example of this is the 00:19:32.150 --> 00:19:35.829 I2C bus, which is a wildly common bidirectional 00:19:35.829 --> 00:19:38.170 communication standard used to connect sensors 00:19:38.170 --> 00:19:40.710 and microcontrollers. OK, so how does an open 00:19:40.710 --> 00:19:42.549 collector room differ from a tri -stay room? 00:19:42.910 --> 00:19:45.809 Well, in an open collector setup, the transmitting 00:19:45.809 --> 00:19:48.750 devices physically cannot drive the communication 00:19:48.750 --> 00:19:52.650 line to a high voltage. Wait! They can't? No. 00:19:53.029 --> 00:19:55.589 They literally lack the internal silicon hardware 00:19:55.589 --> 00:19:59.190 to push a positive voltage onto the wire. The 00:19:59.190 --> 00:20:01.309 bus completely relies on those pull -up resistors 00:20:01.309 --> 00:20:03.990 we just talked about to keep the shared communication 00:20:03.990 --> 00:20:06.250 lines held high by default. Okay, let me try 00:20:06.250 --> 00:20:08.990 a different analogy for this one. So the I2C 00:20:08.990 --> 00:20:11.490 bus is basically a room where the door is held 00:20:11.490 --> 00:20:14.630 wide open by a heavy bungee cord, the pull -up 00:20:14.630 --> 00:20:16.910 resistor. Okay, I like it. Anyone in the room 00:20:16.910 --> 00:20:19.230 can grab the handle and pull the door shut to 00:20:19.230 --> 00:20:22.630 signal a zero, but nobody in the room is physically 00:20:22.630 --> 00:20:25.269 capable of pushing the door wider open. That 00:20:25.269 --> 00:20:27.890 visual works perfectly. To communicate a zero, 00:20:28.109 --> 00:20:30.970 you actively pull against the bungee cord. To 00:20:30.970 --> 00:20:33.170 communicate a one, you don't push, you just let 00:20:33.170 --> 00:20:35.069 go of the handle. You just let go. Yeah, you 00:20:35.069 --> 00:20:37.450 let your output float and the bungee cord, the 00:20:37.450 --> 00:20:41.150 resistor, snaps the door back open. That's incredibly 00:20:41.150 --> 00:20:43.509 elegant because think about the short circuit 00:20:43.509 --> 00:20:46.349 problem from earlier. If device A tries to send 00:20:46.349 --> 00:20:50.029 a zero, it pulls the door shut. If device B gets 00:20:50.029 --> 00:20:52.529 confused and also tries to communicate at the 00:20:52.529 --> 00:20:55.589 exact same time, The worst thing it can do is 00:20:55.589 --> 00:20:58.170 also grab the handle and pull the door shut or 00:20:58.170 --> 00:21:01.250 just let go. It entirely prevents bus contention 00:21:01.250 --> 00:21:04.690 by design. No two devices can ever short -circuit 00:21:04.690 --> 00:21:07.430 the system by driving high and low simultaneously 00:21:07.430 --> 00:21:10.269 because nobody has the physical ability to drive 00:21:10.269 --> 00:21:12.829 high. That solves the whole problem. Now in the 00:21:12.829 --> 00:21:16.190 old days microcontrollers used to have very rigid 00:21:16.190 --> 00:21:19.589 fixed pins. A pin was either a tri -state push 00:21:19.589 --> 00:21:22.059 -pull output or an open collector and you had 00:21:22.059 --> 00:21:24.559 to buy the right chip for the job. But the sources 00:21:24.559 --> 00:21:27.359 say modern microcontrollers are incredibly flexible, 00:21:27.519 --> 00:21:29.839 right? They have general purpose input output 00:21:29.839 --> 00:21:32.539 pins that can be programmed via software to be 00:21:32.539 --> 00:21:34.740 any of those configurations on the fly. Yeah, 00:21:34.839 --> 00:21:37.319 which is an absolute dream for modern electronics 00:21:37.319 --> 00:21:40.000 design. It offers incredible versatility. But 00:21:40.000 --> 00:21:42.240 I do have one final piece of pushback here. Let's 00:21:42.240 --> 00:21:45.140 hear it. If tristate logic is so phenomenal for 00:21:45.140 --> 00:21:47.200 shared motherboards and open collectors are so 00:21:47.200 --> 00:21:50.259 great for sensors, why does the article explicitly 00:21:50.259 --> 00:21:52.640 warn that tristate logic is not recommended for 00:21:52.640 --> 00:21:55.559 on -ship connections? I mean, why would engineers 00:21:55.559 --> 00:21:58.700 completely ditch this elegant system inside the 00:21:58.700 --> 00:22:01.299 actual microscopic silicon of a processor and 00:22:01.299 --> 00:22:03.920 use something called multiplexers instead? That 00:22:03.920 --> 00:22:06.220 warning really comes down to the staggering difference 00:22:06.220 --> 00:22:09.279 in scale and the rigorous math required to build 00:22:09.279 --> 00:22:12.279 modern chips. Scale and math, okay. connecting 00:22:12.279 --> 00:22:14.619 different separate chips on a printed circuit 00:22:14.619 --> 00:22:17.359 board interchip communication tri -state is perfect. 00:22:17.740 --> 00:22:20.460 But inside the microscopic silicon of a single 00:22:20.460 --> 00:22:23.579 processor on chip communication things operate 00:22:23.579 --> 00:22:27.099 at blistering Gigahertz speeds. And the physical 00:22:27.099 --> 00:22:30.000 rules change at that microscopic level. The rules 00:22:30.000 --> 00:22:33.000 of verification change. Fabricating a modern 00:22:33.000 --> 00:22:35.359 silicon wafer takes months and costs hundreds 00:22:35.359 --> 00:22:38.140 of millions of dollars. If a microscopic signal 00:22:38.140 --> 00:22:40.500 arrives at its destination, even a fraction of 00:22:40.500 --> 00:22:43.039 a picosecond late, the processor might calculate 00:22:43.039 --> 00:22:46.359 2 plus 2 equals 5. Oh, wow. The entire chip is 00:22:46.359 --> 00:22:48.700 garbage. So before they ever manufacture the 00:22:48.700 --> 00:22:51.299 chip, engineers run a massive software simulation 00:22:51.299 --> 00:22:53.940 called static timing analysis. So they mathematically 00:22:53.940 --> 00:22:56.680 prove that Every single signal will arrive exactly 00:22:56.680 --> 00:22:58.720 when it's supposed to, down to the picosecond. 00:22:58.980 --> 00:23:02.059 They have to. But a shared internal bus with 00:23:02.059 --> 00:23:04.859 multiple tri -state drivers means the physical 00:23:04.859 --> 00:23:07.799 path the signal takes changes dynamically depending 00:23:07.799 --> 00:23:09.900 on who is talking and who is in high Z. Right, 00:23:09.980 --> 00:23:12.019 it's constantly shifting. It introduces an it 00:23:12.019 --> 00:23:15.059 depends variable into the math and static timing 00:23:15.059 --> 00:23:18.759 analysis algorithms absolutely despise it depends. 00:23:19.140 --> 00:23:21.180 It makes mathematical verification incredibly 00:23:21.180 --> 00:23:24.220 difficult if not computationally impossible at 00:23:24.220 --> 00:23:28.180 modern processor speeds. Ah. So dynamic paths 00:23:28.180 --> 00:23:30.519 ruin the math. So instead of having a shared 00:23:30.519 --> 00:23:33.099 wire where chips take turns turning on and off 00:23:33.279 --> 00:23:35.960 They use multiplexers. Right. A multiplexer is 00:23:35.960 --> 00:23:38.380 basically a highly rigid functional switchboard. 00:23:38.839 --> 00:23:41.460 You hardwire every single internal device's output 00:23:41.460 --> 00:23:43.940 into the multiplexer on its own dedicated wire, 00:23:44.220 --> 00:23:46.619 and the multiplexer acts as the sole central 00:23:46.619 --> 00:23:48.819 gatekeeper, physically selecting which input 00:23:48.819 --> 00:23:50.579 gets to proceed to the next stage. So it's much 00:23:50.579 --> 00:23:53.500 more structured. Yes. It requires vastly more 00:23:53.500 --> 00:23:56.059 microscopic wiring, but mathematically the timing 00:23:56.059 --> 00:23:58.720 is 100 % predictable. It proves that in engineering, 00:23:59.019 --> 00:24:00.940 the environment always dictates the solution. 00:24:01.130 --> 00:24:03.450 It really does. I mean, what works on a six -inch 00:24:03.450 --> 00:24:05.750 motherboard will completely ruin a six -millimeter 00:24:05.750 --> 00:24:09.250 microchip. Exactly. So let's look back at the 00:24:09.250 --> 00:24:11.009 journey we've just taken through your sources 00:24:11.009 --> 00:24:13.970 today. We started by dismantling the simplistic 00:24:13.970 --> 00:24:17.869 myth of purely binary ones and zeros. We discovered 00:24:17.869 --> 00:24:20.750 the high Z state, this vital ghostly third state 00:24:20.750 --> 00:24:23.470 of total physical disconnection that acts as 00:24:23.470 --> 00:24:26.130 the ultimate traffic controller for our hardware. 00:24:26.430 --> 00:24:29.210 We saw how memory chips perform that delicate 00:24:29.210 --> 00:24:32.109 latency -saving dance between output enable and 00:24:32.109 --> 00:24:34.670 chip select, balancing power consumption against 00:24:34.670 --> 00:24:37.630 wake -up times. And we battled the messy analog 00:24:37.630 --> 00:24:40.509 physical reality of floating wires and unintentional 00:24:40.509 --> 00:24:43.589 batteries using weak spring resistors and Intel's 00:24:43.589 --> 00:24:46.109 sustained tri -state trick. Right. And finally, 00:24:46.109 --> 00:24:48.490 we saw how the rules completely rewrite themselves 00:24:48.490 --> 00:24:51.069 again with the bungee -cord logic of open collectors 00:24:51.069 --> 00:24:53.569 and the predictable math of multiplexers. It 00:24:53.569 --> 00:24:55.950 is just an absolutely staggering amount of unseen 00:24:56.330 --> 00:24:58.569 And it is all happening completely invisibly 00:24:58.569 --> 00:25:00.670 to the user. That is the wildest part for me. 00:25:00.869 --> 00:25:02.829 I really want you, the listener, to think about 00:25:02.829 --> 00:25:04.650 this the next time you sit down at your laptop 00:25:04.650 --> 00:25:09.099 or pick up your phone. Every single time you 00:25:09.099 --> 00:25:11.740 press a glass screen, every time you type a letter 00:25:11.740 --> 00:25:15.539 on a keyboard or save a photo, this wildly elaborate 00:25:15.539 --> 00:25:19.480 microscopic choreography of devices waking up, 00:25:19.720 --> 00:25:22.740 forcefully taking control and gracefully disconnecting 00:25:22.740 --> 00:25:25.480 into the void is happening billions of times 00:25:25.480 --> 00:25:28.140 a second inside your device. All perfectly synchronized, 00:25:28.259 --> 00:25:30.299 all just to keep the wires from burning up. And 00:25:30.299 --> 00:25:32.240 if we step back, I think there is a profound 00:25:32.240 --> 00:25:35.019 broader takeaway here beyond just the silicon 00:25:35.019 --> 00:25:39.069 and copper. What's that? closely, our most advanced 00:25:39.069 --> 00:25:41.769 high -speed technology relies absolutely on a 00:25:41.769 --> 00:25:43.789 dedicated state of disconnection. That's true. 00:25:43.930 --> 00:25:46.849 The entire system only functions because individual 00:25:46.849 --> 00:25:49.869 components have the baked inability to actively 00:25:49.869 --> 00:25:52.849 step back, go silent, and let others speak solely 00:25:52.849 --> 00:25:55.970 to prevent total system chaos. I love that. It 00:25:55.970 --> 00:25:58.150 really makes you wonder... If the most complex 00:25:58.150 --> 00:26:00.490 processors in the world require a dedicated state 00:26:00.490 --> 00:26:03.130 of disconnection just to survive, maybe there's 00:26:03.130 --> 00:26:05.549 a lesson there for our always connected, always 00:26:05.549 --> 00:26:08.410 shouting human networks, too. Thanks for joining 00:26:08.410 --> 00:26:10.190 us on this deep dive. We'll see you next time.