WEBVTT

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You know, there's a phrase that I think pretty

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much every single one of us has used at some

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point. Oh, absolutely. Usually it's when you

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are a teenager rolling your eyes at your parents.

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Or maybe it's just like, you know, 5 p .m. on

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a Friday and you are completely burned out. Yeah,

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I know exactly the feeling you're talking about.

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That phrase is, I don't care. It is a classic.

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It's the universal signal for apathy. Usually

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implies... laziness or checking out or just,

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you know, giving up on whatever the problem is.

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Exactly. It sounds like you're quitting. But

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and this is really why I love digging into these

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technical stacks we get for the show in the world

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of computer engineering and digital logic saying,

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I don't care, isn't lazy at all. Not even a little

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bit. It's actually a superpower. It is a strategic

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weapon. It really is. It's a fundamental pillar

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of efficiency. Because if computers cared about

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every single theoretical possibility, they would

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be incredibly slow, they'd be massive, and they'd

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probably overheat in about 10 seconds. So today

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we are doing a deep dive into don't care terms.

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And no, for you listening, that isn't a list

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of people who ghosted me. Let's hope not. It

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is a very specific engineering concept that basically

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allows our devices to function at the speeds

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we expect. But, and here's the twist we are going

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to get to a bit later, if you aren't careful

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with the things you don't care about, they can

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actually come back to haunt you in some pretty

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catastrophic ways. That's the core tension of

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this entire field. It's about knowing what matters

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and strategically ignoring what doesn't so you

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can build a better system. But if you ignore

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the wrong thing, well, you end up in what the

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documentation literally calls a walled garden

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of error states. Which, you know. Sounds lovely,

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but is actually a total nightmare. A complete

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nightmare. Yes. So we have a great stack of source

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material today. We've got technical documentation,

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some encyclopedic records on digital logic design,

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and a bunch of files specifically focusing on

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Boolean functions and circuit minimization. It's

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a really comprehensive pile of sources. It is.

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And our mission today is to figure out how engineers

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decide what to ignore to make things faster,

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cheaper, and smaller, and what happens when it

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all goes wrong. Sounds like a plan. Let's start.

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at the beginning with the definition when a logic

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designer says don't care what are they actually

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looking at on their screen so in the strictest

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definition from the encyclopedic records we are

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looking at a boolean function right basically

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the math of logic the zeros and the ones right

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a don't care term which is often abbreviated

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just as dc is an input sequence a specific series

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of bits for a boolean function where the output

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effectively does not matter okay let's make that

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concrete for the listener the system receives

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a message like a specific pattern of bits and

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the designer basically says if you hear the specific

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sequence i really don't care what you do precisely

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But they don't say that out of laziness. It's

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usually because that specific input sequence

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is totally irrelevant to the function at hand.

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Right. The history of this is actually great

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because the names for this concept in the older

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literature are incredibly descriptive. You will

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see them called redundancies or irrelevancies.

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I actually found a few more colorful ones in

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the notes that I really liked. Vacuous combinations.

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Which sounds a bit harsh, honestly. Like an insult

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you would hear in a Victorian novel. You vacuous

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combinations. Exactly. Or they call them forbidden

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combinations. And my personal favorite, logical

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remainders. It sounds like a progressive rock

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band. It really does. But forbidden is actually

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the best hint at what's going on here. The reason

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the designer doesn't care. about the output for

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these terms is that they have the freedom to

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choose it arbitrarily. Now explain that freedom,

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because usually in engineering, precision is

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everything, right? You don't just get to choose

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your output on a whim. If I press A on my keyboard,

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I want an A to pop up, not a Q, just because

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the engineer felt like it. Well, think of it

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this way. If I tell the circuit, I don't care

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if the output is a 1 or a 0 for this specific

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input. That gives the mathematical model flexibility.

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I can assign it a 1 or I can assign it a 0. And

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I get to choose whichever one makes the overall

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math equation simple. Oh, I see. So it isn't

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just ignoring it. It's using it as a tool. It

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acts like a wild card. Exactly. It is a wild

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card. By picking the most convenient output for

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those don't care spots, we achieve minimization.

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Minimization. Right. We can make the circuit

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simplest, smallest, fastest. We can make it cheapest

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to manufacture, or we can use it to reduce power

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consumption. So if assigning a 1 to that don't

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care spot allows me to group a bunch of other

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signals together and maybe, I don't know, delete

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a physical transistor or remove a wire entirely,

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I just do it. You do it immediately. In the old

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days, this saved actual physical bulky components.

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Today, inside a microscopic silicon chip, it

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saves space and energy. Every single logic gate

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you remove means less heat generated by the processor.

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OK, let's unpack this minimization concept a

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bit more, because I think when people hear minimization,

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they might think cutting corners like, oh, we

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didn't bolt the bolts on the bridge to save money.

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But you're saying it's really about pure optimization.

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Right. It's elegance, not laziness. And to truly

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understand that, we have to look at the logic.

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of ignoring things. There is a subtle but absolutely

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critical distinction in the source material between

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a pure don't care term and what is called a can't

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happen term. A can't happen term. That sounds

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pretty definitive. It is definitive. A can't

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happen term is an input sequence that we know,

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either physically or logically, will simply never

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occur in the normal operation of the system.

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Give me a real -world analogy for that because

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input sequence can feel a little abstract if

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you aren't staring at code all day. Okay, think

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about a standard digital calendar. Okay. You

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have inputs for the month and inputs for the

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day. Right. The input for the month is February

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and the input for the day is the 30th. That is

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a can't happen term. Oh, because February 30th

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doesn't exist. Exactly. So if you are designing

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the logic for what that calendar application

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should do, you do not need to write a specific

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complex rule for February 30th. You don't need

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to say if Feb 30, then display a giant error

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message. You just don't care. Because the user

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physically can't select it from the dropdown

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anyway? Ideally, yes. So seeing February 30th

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is a can't happen event. Okay, so if I'm the

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designer and I have this wildcard freedom, do

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I just let the system crash if it somehow happens?

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Or do I actively use it? Well, here is the key

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takeaway from the encyclopedias. To a logic designer,

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a can't happen term and a don't care term are

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treated the exact same way. They are. Yes. They

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were both just opportunities for optimization.

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If you know an input can't happen, you don't

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care what the output would be if it did happen.

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Because theoretically, it is never, ever going

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to happen. In theory. And that's exactly where

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the optimization comes in. Engineers use specific

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tools to visualize all this. The sources mention

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methods like Carnivage maps. Ah, K -maps. I saw

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these in the documentation. They look like little

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grids of squares. It honestly looks like a Sudoku

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puzzle. It's a bit like Sudoku, or maybe Tetris.

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You map out your ones and zeros on this grid.

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Each square represents a combination of inputs.

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And then you have these blank spots on the board.

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Those are the don't cares. And the goal is to

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circle groups of them, right? Yes. The goal of

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the KMAP is to draw boxes around groups of ones

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to simplify the logic. And the mathematical rule

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is the bigger the box you can draw, the simpler

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the resulting circuit becomes. So if I have a

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don't care square sitting right next to a bunch

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of one squares. You should pretend the don't

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care is a one. Now your box is bigger. Your logic

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is simpler. You have just saved a logic gate.

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That is incredibly satisfying. It's like connecting

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the dots, but you get to draw extra dots wherever

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you want just to make the picture look better.

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That is a perfect way to describe it. There is

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also the Quine -McCluskey algorithm, which is

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heavily featured in the notes. That's essentially

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just an algebraic way to do the exact same thing

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for much more complex systems where a grid is

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just way too hard to draw by hand. I do want

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to touch on a bit of the historical context here

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because the notes mention a guy named Seymour

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Ginsburg back in 1958. This seemed like a massive

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turning point in how we actually understand this

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efficiency. Yes, Ginsburg. This part is fascinating

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because it really highlights the physical limits

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of early computing. In 1958, they simply didn't

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have the processing power we have now to design

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chips. They were working with much clearer constraints.

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Right, because today we just assume computers

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can optimize anything instantly. You type code,

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and the compiler fixes your mess behind the scenes.

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Back then, Ginsburg proved something that was

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actually quite counterintuitive. He was looking

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at finite state machines. Those are basically

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systems that move step by step from state A to

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state B. Okay. He showed that just because you

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minimize the states, like reducing the number

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of actual steps it takes to do a job, it doesn't

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necessarily mean you have minimized the logic

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elements. Wait, that sounds completely backwards.

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If I have fewer steps, shouldn't I automatically

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have less hardware? If I build a machine with

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three gears instead of four, it should be a smaller

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machine. In mechanics, yes. But in logic, not

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always. Sometimes, describing a shortcut takes

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a much more complex vocabulary than just taking

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the long way around. Oh, I get it. Imagine trying

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to explain a shortcut through a city that involves

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six very specific left turns through back alleys

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versus just saying, stay on the highway. The

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highway is technically longer, so it has more

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states, but the instruction is much simpler,

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less logic. That makes perfect sense. So Ginsburg

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proved mathematically that simple behavior doesn't

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always equal simple wiring. Exactly. And he pointed

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out a major historical limitation. Calculating

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the absolute perfect direct minimization using

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these don't care conditions for large systems

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was computationally impractical in 1958. They

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fully understood the theory, but they couldn't

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always brute force the perfect solution. So they

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basically had to make trade -offs. They knew

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they were leaving some efficiency on the table

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because they just didn't have the computers to

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calculate how to build better computers. Which

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is humbling, honestly. It shows that even the

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concept of strategically ignoring things requires

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a massive amount of calculation to get right.

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Let's try to really ground this for the listener.

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We've been talking a lot about logic and sequences

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and algorithms. Can we give a concrete example

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of where a don't care term actually lives inside

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a gadget that I might recognize? The absolute

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classic example and the one the source material

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highlights heavily is BCD, binary coded decimal.

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Binary coded decimal. Break that down for us.

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So ideally, computers just like binary, pure

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ones and zeros. But humans, we like. decimal.

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We like our digits 0 through 9. BCD is a specific

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way of encoding those human -friendly digits

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using exactly four bits of binary code. Okay,

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four bits. So that's 0, 0, 0, 0, 0, 0, 0, 1,

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all the way up to weight. Four bits. That's 2

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to the power of 4. That is 16 combinations. You

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got it. Four bits can count from 0 up to 15.

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That's 16 possible combinations. But for BCD,

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which represents just a single decimal digit,

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we only actually need 0 through 9. So what happens

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to the binary codes for 10, 11, 12, 13, 14, and

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15? They are the don't care terms. The sources

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refer to them as pseudotetrates. Pseudotetrades.

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That sounds like a dinosaur. Or maybe a very

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specific weird geometric shape. Look out! A wild

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pseudotetrade appeared. It does sound ancient.

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But it simply means they are combinations of

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four bits that in the specific language of BCD

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are complete nonsense. They are totally unused.

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So if I'm building a circuit for, say, an old

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school alarm clock with those glowing red seven

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segment displays. Perfect example. Everyone knows

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those clocks. The displays have seven little

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LED light bars arranged in a figure eight pattern.

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To make the number one, you light up two bars

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on the right. To make the number eight, you light

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up all seven bars. Right. Now imagine you are

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the engineer designing the circuit that controls

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just the lower left vertical bar of that display,

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just that one little line. Okay. You need to

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tell that bar exactly when to turn on. It turns

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on for the number zero, the number two, the number

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six, the number eight. And it stays off for one,

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three, four, five, seven, and nine. Correct.

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But what about inputs 10 through 15? Well, the

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clock is only ever supposed to show zero to nine.

00:12:19.070 --> 00:12:21.730
If my bedside clock shows a 12 in a single digit

00:12:21.730 --> 00:12:24.070
spot, something is very physically wrong with

00:12:24.070 --> 00:12:27.169
my bedroom. So the chip should never, ever receive

00:12:27.169 --> 00:12:30.610
a 12. Exactly. It's a can't happen term. So for

00:12:30.610 --> 00:12:33.950
the inputs 10 through 15, which is binary, 1010

00:12:33.950 --> 00:12:37.409
through 11111, the designer just says, I don't

00:12:37.409 --> 00:12:41.100
care. If the chip did somehow receive a 12, it

00:12:41.100 --> 00:12:43.139
literally does not matter if that lower left

00:12:43.139 --> 00:12:45.379
bar lights up or not because the user is never

00:12:45.379 --> 00:12:47.120
supposed to be in a situation to see it. And

00:12:47.120 --> 00:12:49.539
by saying I don't care, the math for that lower

00:12:49.539 --> 00:12:53.269
left bar gets easier. So much easier. The Boolean

00:12:53.269 --> 00:12:56.009
function can be simplified significantly. Without

00:12:56.009 --> 00:12:57.950
the don't cares, the logic equation might be

00:12:57.950 --> 00:12:59.889
huge because you have to explicitly tell it to

00:12:59.889 --> 00:13:03.830
be 0 off f for 10, 0 off for 11, 0 off for 12.

00:13:04.250 --> 00:13:07.330
But if we treat those unused numbers as wildcards,

00:13:07.629 --> 00:13:10.330
we can simplify the equation down to practically

00:13:10.330 --> 00:13:13.409
nothing. You save actual transistors on the chip.

00:13:13.629 --> 00:13:15.389
That is really cool. It's kind of like cleaning

00:13:15.389 --> 00:13:17.230
your room by shoving everything into the closet,

00:13:17.330 --> 00:13:19.110
but because nobody is ever allowed to open the

00:13:19.110 --> 00:13:21.509
closet, the room is technically clean? In a way,

00:13:21.610 --> 00:13:25.389
yes. You're optimizing the visible space by utilizing

00:13:25.389 --> 00:13:28.049
the forbidden space. And there is actually another

00:13:28.049 --> 00:13:31.289
super quirky example of this in vintage hardware.

00:13:31.830 --> 00:13:34.850
Write -only registers. I saw this in the notes

00:13:34.850 --> 00:13:37.610
and it confused me. A register is basically a

00:13:37.610 --> 00:13:40.029
memory slot. So this is a slot that you can write

00:13:40.029 --> 00:13:42.610
data to, but you literally cannot read data from.

00:13:42.649 --> 00:13:44.730
That sounds useless. How do you know what's in

00:13:44.730 --> 00:13:47.210
it? You don't. It is strictly one -way communication.

00:13:47.789 --> 00:13:51.009
In older hardware... Reading data back out required

00:13:51.009 --> 00:13:54.210
extra logic gates. It needed extra wires, extra

00:13:54.210 --> 00:13:56.929
multiplexers. If the designer desperately needed

00:13:56.929 --> 00:13:59.549
to save space or cost and the software didn't

00:13:59.549 --> 00:14:01.950
strictly need to check what it just wrote, they

00:14:01.950 --> 00:14:04.470
would just completely leave out the read circuitry.

00:14:04.549 --> 00:14:06.450
So what happens if a programmer makes a mistake

00:14:06.450 --> 00:14:08.289
and tries to read it anyway? Like, hey, computer,

00:14:08.389 --> 00:14:10.149
what number's in that box? You get a don't care

00:14:10.149 --> 00:14:12.850
result. You just get garbage data. So the computer

00:14:12.850 --> 00:14:14.509
basically just shrugs and hands you whatever

00:14:14.509 --> 00:14:17.159
random electricity happened to be nearby. Basically,

00:14:17.240 --> 00:14:20.059
yeah. It might return all zeros, all ones, or

00:14:20.059 --> 00:14:23.279
just pure static noise. It is a direct consequence

00:14:23.279 --> 00:14:26.659
of don't care optimizations. The engineers actively

00:14:26.659 --> 00:14:29.200
traded functionality, the ability to read for

00:14:29.200 --> 00:14:31.879
hardware size. The output for read was explicitly

00:14:31.879 --> 00:14:35.539
defined as a don't care. Okay, so we've got a

00:14:35.539 --> 00:14:37.279
good handle on the hardware side, but I want

00:14:37.279 --> 00:14:39.200
to transition to the software side, or at least

00:14:39.200 --> 00:14:41.659
the simulation side of things, because the technical

00:14:41.659 --> 00:14:44.419
docs mention this somewhat mysterious X value.

00:14:44.720 --> 00:14:47.600
Ah, yes, the X factor. This is where things get

00:14:47.600 --> 00:14:49.840
really interesting, and honestly, where the critical

00:14:49.840 --> 00:14:52.620
distinction between simulation and physical reality

00:14:52.620 --> 00:14:55.019
becomes so important. So in hardware description

00:14:55.019 --> 00:14:58.440
languages, things like Verilog or VHDL, which

00:14:58.440 --> 00:15:00.720
engineers use to code the hardware before it's

00:15:00.720 --> 00:15:02.919
actually built in a factory, you have zero, you

00:15:02.919 --> 00:15:05.919
have one, and you have... X. Right. In multivalued

00:15:05.919 --> 00:15:08.799
logic for Verilog, it's literally just X. In

00:15:08.799 --> 00:15:12.059
VHDL, it can be X for a forced unknown or sometimes

00:15:12.059 --> 00:15:15.139
a W for a weak unknown. A weak unknown. That

00:15:15.139 --> 00:15:16.740
sounds like me trying to remember where I parked

00:15:16.740 --> 00:15:18.799
at the grocery store. But what does X actually

00:15:18.799 --> 00:15:20.799
mean when you're running a simulation on a screen?

00:15:21.059 --> 00:15:24.539
In a computer simulation of a chip, an X usually

00:15:24.539 --> 00:15:27.600
represents a problem or a transition state. It

00:15:27.600 --> 00:15:29.299
might mean you have a flip -flop, a little memory

00:15:29.299 --> 00:15:31.399
storage unit that simply hasn't settled yet.

00:15:31.419 --> 00:15:34.590
It's in flux. Okay. Or, and this is worse, it

00:15:34.590 --> 00:15:36.389
could mean you have two different sources trying

00:15:36.389 --> 00:15:38.490
to drive the exact same signal at the same time.

00:15:39.110 --> 00:15:41.330
One wire is trying to say zero and the other

00:15:41.330 --> 00:15:43.090
wire is trying to say one. So it's a conflict.

00:15:43.230 --> 00:15:46.190
A massive conflict. The simulator basically throws

00:15:46.190 --> 00:15:48.789
up its hands and says, X, I don't know who wins.

00:15:49.509 --> 00:15:51.629
It's a very useful way for the simulation to

00:15:51.629 --> 00:15:54.289
tell the engineer, hey, your logic is ambiguous

00:15:54.289 --> 00:15:56.970
right here. And I think here is where it gets

00:15:56.970 --> 00:15:59.029
really interesting for anyone trying to wrap

00:15:59.029 --> 00:16:01.850
their head around this. You can't have an X in

00:16:01.850 --> 00:16:04.649
real life, can you? If I took a physical voltmeter

00:16:04.649 --> 00:16:08.250
to a physical wire inside my laptop motherboard,

00:16:08.690 --> 00:16:13.049
the dial wouldn't say X. No, you cannot measure

00:16:13.049 --> 00:16:15.149
an X. And this is a concept that actually trips

00:16:15.149 --> 00:16:17.330
up a lot of students and even junior engineers.

00:16:17.509 --> 00:16:20.649
An X value simply does not exist in synthesized

00:16:20.649 --> 00:16:23.429
hardware in reality. Because physics is physics.

00:16:23.629 --> 00:16:26.070
There is either a voltage on the wire or there

00:16:26.070 --> 00:16:28.309
isn't. It's not magic. It's not Schrodinger's

00:16:28.309 --> 00:16:31.210
cat. Exactly. The voltage is always either a

00:16:31.210 --> 00:16:33.629
zero or a one, assuming it's within the logic

00:16:33.629 --> 00:16:36.769
thresholds. The real problem is, because of that

00:16:36.769 --> 00:16:39.029
conflict or that unsettled state we saw in the

00:16:39.029 --> 00:16:41.570
simulation, we as the observers don't actually

00:16:41.570 --> 00:16:44.389
know which one it is. It's just a ghost in the

00:16:44.389 --> 00:16:47.509
machine. It truly is. The specific zero or one

00:16:47.509 --> 00:16:51.169
is not determinable from the inputs. So in the

00:16:51.169 --> 00:16:53.730
real physical world, the chip isn't outputting

00:16:53.730 --> 00:16:56.860
a magical X state. It is outputting a 1 or a

00:16:56.860 --> 00:16:59.440
0, but it might be flickering rapidly or it might

00:16:59.440 --> 00:17:01.679
be stuck and we just can't predict it based on

00:17:01.679 --> 00:17:03.960
the logic rules we wrote. That feels a little

00:17:03.960 --> 00:17:06.339
unsettling, to be honest. We build these machines

00:17:06.339 --> 00:17:09.400
to be these precise, perfectly logical beasts,

00:17:09.559 --> 00:17:12.480
but deep down there are these pockets of we just

00:17:12.480 --> 00:17:14.680
don't know. And that leads us directly to the

00:17:14.680 --> 00:17:17.339
truly dangerous part of don't care terms. Because

00:17:17.339 --> 00:17:20.180
sometimes what we think implies I don't care

00:17:20.180 --> 00:17:22.900
actually turns into I really should have cared.

00:17:23.059 --> 00:17:25.609
Right. Let's get into the danger zone. So we

00:17:25.609 --> 00:17:27.569
established earlier that can't happen terms are

00:17:27.569 --> 00:17:30.009
treated as don't cares. We optimize the chip,

00:17:30.049 --> 00:17:33.089
assuming they will never, ever occur. But what

00:17:33.089 --> 00:17:35.130
if a can't happen condition actually does happen?

00:17:35.329 --> 00:17:38.670
This is the absolute nightmare scenario for reliability

00:17:38.670 --> 00:17:42.069
engineers. And this is especially risky in circuits

00:17:42.069 --> 00:17:44.569
that involve feedback. Things like state machines,

00:17:44.950 --> 00:17:46.950
where the next step the machine takes depends

00:17:46.950 --> 00:17:49.960
entirely on the previous step it just took. Okay,

00:17:50.019 --> 00:17:52.420
so let's visualize this for the listener. Normally,

00:17:52.480 --> 00:17:54.539
the machine bounces happily between state A,

00:17:54.619 --> 00:17:57.500
state B, and state C. It is never supposed to

00:17:57.500 --> 00:18:00.500
go to state D. So the engineers optimized state

00:18:00.500 --> 00:18:03.079
D completely out of existence. They treated it

00:18:03.079 --> 00:18:05.599
as a don't care. Correct. We didn't build a logic

00:18:05.599 --> 00:18:07.759
path out of state D because we confidently assumed

00:18:07.759 --> 00:18:10.480
we would never get into state D. But how does

00:18:10.480 --> 00:18:13.319
the physical machine get to state D if it's supposed

00:18:13.319 --> 00:18:15.980
to be mathematically impossible? The source material

00:18:15.980 --> 00:18:19.589
lists a few major culprits. Power up is a really

00:18:19.589 --> 00:18:21.809
big one. When you first turn a device on, for

00:18:21.809 --> 00:18:24.390
just a split second, all the voltage levels across

00:18:24.390 --> 00:18:26.829
the board are stabilizing. The flip -flops might

00:18:26.829 --> 00:18:28.910
wake up in a completely random state. So you

00:18:28.910 --> 00:18:31.049
turn on your smart toaster, and for one tiny

00:18:31.049 --> 00:18:33.789
millisecond, it wakes up and thinks it is in

00:18:33.789 --> 00:18:36.009
a state that doesn't logically exist. Exactly.

00:18:36.049 --> 00:18:39.210
It wakes up in that forbidden state D. Another

00:18:39.210 --> 00:18:41.990
cause could be that the power supply fluctuated.

00:18:42.509 --> 00:18:46.140
And the other causes are even more exotic. Things

00:18:46.140 --> 00:18:48.819
like electrical noise, extreme heat, or even

00:18:48.819 --> 00:18:52.039
cosmic radiation. Cosmic radiation. I love that

00:18:52.039 --> 00:18:54.819
actual space particles can fly through the atmosphere,

00:18:55.019 --> 00:18:57.119
flip a single bit in my computer, and cause a

00:18:57.119 --> 00:18:59.440
don't -care error. It sounds like pure science

00:18:59.440 --> 00:19:02.200
fiction. It absolutely happens. In the industry,

00:19:02.339 --> 00:19:04.980
it's called a soft error. A high -energy particle

00:19:04.980 --> 00:19:07.900
hits a microscopic transistor and literally flips

00:19:07.900 --> 00:19:11.220
a zero to a one. And here's the dire consequence.

00:19:11.599 --> 00:19:14.420
If that physical flip pushes the machine into

00:19:14.420 --> 00:19:16.259
a state it was never supposed to be in a forbidden

00:19:16.259 --> 00:19:19.200
input, it might get entirely stuck. The source

00:19:19.200 --> 00:19:21.839
text uses a very poetic phrase for this specific

00:19:21.839 --> 00:19:24.519
lockup. It calls it a walled garden of states.

00:19:24.819 --> 00:19:27.740
It is a beautiful image, isn't it? But a terrible,

00:19:27.779 --> 00:19:30.599
terrible situation for a circuit. Imagine the

00:19:30.599 --> 00:19:32.819
machine accidentally lands in one of those can't

00:19:32.819 --> 00:19:35.769
-happen states. Because we treated it as a don't

00:19:35.769 --> 00:19:38.309
care to save space, we didn't program a way out.

00:19:38.349 --> 00:19:40.130
We didn't give it an instruction that says, if

00:19:40.130 --> 00:19:42.289
you find yourself here, go back to start. We

00:19:42.289 --> 00:19:44.829
just left the logic completely undefined. Yes.

00:19:45.369 --> 00:19:47.609
So the machine might look at its internal logic

00:19:47.609 --> 00:19:50.869
table, see that the next step from this impossible

00:19:50.869 --> 00:19:54.109
state is just another impossible state. And it

00:19:54.109 --> 00:19:56.869
just bounces around in this walled garden of

00:19:56.869 --> 00:19:59.769
invalid states, unable to ever get back to normal

00:19:59.769 --> 00:20:02.529
operation. That's a hardware lockup. That is

00:20:02.529 --> 00:20:04.730
your computer freezing completely and needing

00:20:04.730 --> 00:20:07.630
you to pull the plug for a hard reboot. It is

00:20:07.630 --> 00:20:10.950
literally lost in a logic maze that has no physical

00:20:10.950 --> 00:20:13.950
exit. That is terrifying for anything mission

00:20:13.950 --> 00:20:16.910
critical. I mean, if my smart toaster freezes

00:20:16.910 --> 00:20:18.970
in a walled garden, fine, I get bumped toast.

00:20:19.329 --> 00:20:22.730
But what if it's a pacemaker or a communications

00:20:22.730 --> 00:20:25.349
satellite or the anti -lock breaks on a car?

00:20:25.549 --> 00:20:27.890
Exactly. That is where the stakes completely

00:20:27.890 --> 00:20:30.549
change. So responsible designers have to ensure

00:20:30.549 --> 00:20:32.269
that can't -happen states are truly impossible.

00:20:32.849 --> 00:20:35.950
Or, if the safety is critical, they simply cannot

00:20:35.950 --> 00:20:38.549
use those states for optimization. They have

00:20:38.549 --> 00:20:40.470
to leave the efficiency on the table. So you

00:20:40.470 --> 00:20:42.529
have to sacrifice the smaller chip size. You

00:20:42.529 --> 00:20:44.289
have to leave the extra logic gate on the board

00:20:44.289 --> 00:20:46.769
just in case. You have to. You design what the

00:20:46.769 --> 00:20:48.829
documents call don't -care alarms. An alarm,

00:20:48.950 --> 00:20:50.869
like a physical siren goes off. Essentially,

00:20:50.970 --> 00:20:53.509
it's logic that detects if the machine enters

00:20:53.509 --> 00:20:56.380
a forbidden state. It flags an emergency signal

00:20:56.380 --> 00:20:59.299
to the main processor. Or, even more commonly,

00:20:59.500 --> 00:21:01.859
you design the logic so that all those unused

00:21:01.859 --> 00:21:04.539
states automatically transition back to a known,

00:21:04.720 --> 00:21:07.660
safe, normal state. These are called transitory

00:21:07.660 --> 00:21:11.339
states. Oh, like self -healing logic. Yes. It

00:21:11.339 --> 00:21:13.660
assumes the impossible might actually happen

00:21:13.660 --> 00:21:17.519
due to a cosmic ray or a power surge, and it

00:21:17.519 --> 00:21:21.089
deliberately provides a path home. It explicitly

00:21:21.089 --> 00:21:23.630
says, if you wake up in state D, go immediately

00:21:23.630 --> 00:21:26.809
to state A. It costs more logic, it makes the

00:21:26.809 --> 00:21:28.589
physical chip slightly bigger and more power

00:21:28.589 --> 00:21:30.710
-hungry, but it prevents the walled garden scenario

00:21:30.710 --> 00:21:32.769
entirely. So it really just comes down to, how

00:21:32.769 --> 00:21:35.109
much do you trust the universe not to mess with

00:21:35.109 --> 00:21:37.990
your voltages today? Pretty much. If you are

00:21:37.990 --> 00:21:40.190
building a cheap plastic toy that sings when

00:21:40.190 --> 00:21:41.829
you press a button, you optimize everything,

00:21:42.069 --> 00:21:44.029
use all the don't cares, and you risk the lockup.

00:21:44.269 --> 00:21:46.410
If you are building the navigation system for

00:21:46.410 --> 00:21:48.759
an airplane, you build the path home. This has

00:21:48.759 --> 00:21:50.400
been a really enlightening look at something

00:21:50.400 --> 00:21:52.359
that sounds so dismissive on the surface, don't

00:21:52.359 --> 00:21:54.700
care. But really, it is entirely about efficiency.

00:21:54.980 --> 00:21:57.400
It is. It's about recognizing that not every

00:21:57.400 --> 00:22:00.339
single input requires a specific, thoughtful

00:22:00.339 --> 00:22:04.160
response. Strategically ignoring the impossible

00:22:04.160 --> 00:22:07.519
allows the possible to run smoother, faster,

00:22:07.759 --> 00:22:10.900
and cheaper. It's focusing purely on what matters.

00:22:11.160 --> 00:22:13.519
Exactly. But as we learned with the walled gardens,

00:22:13.660 --> 00:22:15.740
you have to be careful because if you ignore

00:22:15.740 --> 00:22:19.200
the wrong thing or if the universe decides to

00:22:19.200 --> 00:22:22.039
force an impossible input on you anyway, you

00:22:22.039 --> 00:22:25.000
end up scrapped. It is the absolute classic engineering

00:22:25.000 --> 00:22:28.470
tension. Optimization versus robustness. You

00:22:28.470 --> 00:22:30.869
can strip everything down to the bare metal to

00:22:30.869 --> 00:22:33.750
make it blazing fast, but you lose that critical

00:22:33.750 --> 00:22:35.930
buffer against the unexpected. Before we go,

00:22:35.990 --> 00:22:37.769
I want to leave you, the listener, with a thought

00:22:37.769 --> 00:22:40.049
about that X value we discussed. You mentioned

00:22:40.049 --> 00:22:42.250
that in reality, X doesn't exist. It is always

00:22:42.250 --> 00:22:43.970
a zero or a one. We just don't know which one

00:22:43.970 --> 00:22:47.359
it is. Right. The physics demands value. The

00:22:47.359 --> 00:22:49.640
universe doesn't do undefined. I feel like there's

00:22:49.640 --> 00:22:52.299
a real life philosophy buried in there. In the

00:22:52.299 --> 00:22:54.660
simulation of our lives, our plans, our daily

00:22:54.660 --> 00:22:57.680
worries, we have all these unknowns. These X

00:22:57.680 --> 00:23:00.259
values where we feel like we are in conflict

00:23:00.259 --> 00:23:02.619
or totally unsettled. We don't know the outcome.

00:23:02.819 --> 00:23:05.240
But in the physical reality of the moment, everything

00:23:05.240 --> 00:23:08.160
already has a value. We are where we are. The

00:23:08.160 --> 00:23:11.039
outcome is already unfolding. We just might not

00:23:11.039 --> 00:23:12.940
have the inputs to determine what it is yet.

00:23:13.059 --> 00:23:15.670
That is... Surprisingly deep for a technical

00:23:15.670 --> 00:23:18.230
discussion about logic gates. But it's true.

00:23:18.410 --> 00:23:20.630
The value is always there, even if the simulator

00:23:20.630 --> 00:23:22.930
in our heads can't quite see it yet. Just don't

00:23:22.930 --> 00:23:25.130
let a cosmic ray knock you into a walled garden

00:23:25.130 --> 00:23:27.769
today. Thanks for joining us for this deep dive.

00:23:27.890 --> 00:23:29.150
Stay curious. We will see you downtime.
